The ambition of semiconductor semiconductor manufacturing facilities is to maximize the number of wafers produced while at the same time maintaining an acceptable mean cycle time of wafers. Throughput needs to be maximized because of the capital intensive equipment used. The mean cycle time needs to be low to ensure a short time-to-market.
For a successful performance improvement regarding cycle time, one needs to know, among others, the mean capacity loss as well as the process time variability for each workstation in a manufacturing line. Capacity loss and variability at workstations are due to disturbances such as machine downs, setup, operator availability, etcetera. At present, in semiconductor manufacturing only capacity losses are quantified through metrics such as the OEE. Quantification of the contribution of variability to the cycle time performance is not covered through the OEE.
Hopp and Spearman introduce in their book Factory Physics (1996, 2000) the term effective process time (EPT) to acknowledge that process times at workstations should be seen from a logistical point of view. That is, they include in the EPT besides raw processing time also waiting time due to disturbances. The advantage of this approach is that both the mean effective process time as well as its coefficient of variation can be considered. For their calculations, Hopp and Spearman assume that the contribution of the individual sources of variability is known. However, in industrial practice this is in general not the case.
In our work on the EPT we take a top-down instead of a bottom-up view. For some years now we are developing new methods to measure effective process times of machines or workstations without the need to quantify all contributing disturbances. Furthermore, we are developing methods to build simple but accurate aggregate models (also called lumped-parameter models or aggregate models) based on the EPT. The EPT can thus be used to carry out a bottleneck analysis, to feed analytical queueing models with EPT distribution parameters (e.g. mean and coefficient of variation), and to arrive at simple but accurate dynamic simulation models.
Our work on the EPT was initiated in 1998. In 2001 we presented our first EPT algorithms for infinitely buffered workstations of single-lot machines. In the years thereafter we intensified our efforts. We started collaboration with the Stochastic Operations Research group at the Department of Mathematics, which resulted in a joint STW project EPT1 on the EPT starting from June 2004. Several students have done their M.Sc thesis work in the context of the EPT research. Some of the developed EPT algorithms are already used in an automotive manufacturing plant.
The EPT (effective process time) is proposed as a new approach for cycle time improvement in a semiconductor manufacturing environment. The EPT provides a new way to compute effective process times at workstations in a factory from operational data such as arrival and departure times at workstations. This data can often easily be made available from the Manufacturing Execution System (MES) of modern semiconductor wafer fabrication plants. Each departure of a lot at the workstation gives a new effective process time realization. The various lot departures thus provide an effective process time distribution for the workstation under consideration from which e.g. mean and variance can easily be obtained. This also allows run-time monitoring of the workstations regarding their effectively installed capacity and variability behavior. Highly variable workstations cause large queues, generally also downstream of the workstation in the line. Since short cycle times are essential in world-class semiconductor manufacturing, the EPT may provide a valuable new tool for factory management.
In addition to using the EPT as a measurement tool, a second advantage that we envision is to facilitate the development of simple but accurate aggregate models of the wafer fab. We see advantages of aggregate modeling on basis of the EPT for static queueing type of models as well as for dynamic discrete-event simulation models. The quality of these models relies on operational data regarding the various process steps. Queueing models typically require first-order (mean) and second-order (variance) information on the processing times, in addition to the arrival distributions at the various workstations. Simulation models are able to incorporate more detailed information on shopfloor realities including machine downs, operators, and recipe issues. The analytical models are typically used in capacity planning; the simulation models typically in issues regarding manufacturing control such as dispatching, line balance, etc. For both types of models, the major difficulty is feeding the models with the correct operational data and to keep the models updated when the fab gradually evolves over time. The EPT provides new opportunities here.
Previous research on EPT focused on specific machine types in isolated workstations, such as single lot machine workstations, and batching machine workstations. In the ongoing STW-EPT project *link* currently assembly lines with finite and lithographic (cascade) type of workstations are being investigated by Kock et al. Furthermore, queueing approximation methods based on the EPT are being developed (van Vuuren et al, 2007), with the aim to arrive at a very efficient but accurate cycle time prediction of queueing networks.
The present aims to make the EPT operational in the environment of a semiconductor wafer fab. Research will be carried out to validate the EPT approach in the context of semiconductor wafer fabrication, and new EPT methods will be developed to enable the application of the EPT concepts in such an environment.
PhD candidate: ir. C.P.L. Veeger